1. Field of the Invention
This invention relates to electrical circuits, and more particularly to a bias circuit for a field effect transistor (FET) switch implemented as an integrated circuit.
2. Description of the Prior Art
In the past, inefficient biasing circuits have been utilized for FET switches in order to provide tolerances for various circuit parameters which have been found to vary due to processing and temperature conditions. These bias circuits have been designed to allow for worst case conditions, and therefore consume considerably more power than would ordinarily be required.
FIG. 1 shows a typical prior art bias circuit for a junction FET (JFET) switch. This circuit has been utilized in the Precision Monolithics, Inc. SSS7510/7511 Quad SPST BI-FET Analog Switch. In this circuit JFET1 functions as a switch element, with the remainder of the circuitry providing a bias to ensure proper switching of JFET1.
The bias circuit includes JFET2, which has its gate and source terminals connected together to a positive bias voltage line V.sup.+ and provides a source of bias current at its drain. The drain current of JFET2 is directed through a series of diode-connected transistors D1, D2 and D3. The base of D3 is connected to the base of a bipolar transistor Q1, whereby Q1 mirrors the current through D3. Q1 serves as a current source for a differential switch having a left branch transistor Q2 and a right branch transistor Q3. The collector of Q2 is connected back to the positive voltage bus through a resistor R1, while the collector of Q3 is connected to the positive voltage bus through diode-connected transistors D4 and D5. Another current source JFET3 has its gate and source connected to the positive voltage bus to provide a source of current for input transistor Q4, the base of which receives a logic input signal at terminal 2.
The source of switch JFET1 is connected to the positive voltage bus through diode-connected transistor D6 and a bipolar transistor Q5, the collector of which is connected to V.sup.+ and the base of which is connected to the opposite end of R1 from V.sup.+. The base of JFET1 is connected by lead 4 to the junction of D4 and Q3.
In operation, the common connection between the gate and source of JFET2 provides a current at the drain of that element. This current is delivered through D3 and mirrored by Q1 to provide a current source for the differential switch Q2-Q3. Assuming it is desired to turn JFET1 OFF, a positive voltage signal is applied to base terminal 2 of Q4, turning that transistor OFF and gating Q2. The base voltage of Q2 exceeds the threshold voltage at the base of Q3 established by its connection to D1, causing the current from Q1 to flow through Q2 and R1 rather than through Q3. The current through R1 establishes a voltage differential across the element with respect to V.sup.+ which is reflected to the source of JFET1, with two diode voltage drops through the base-emitter of Q5 and D6. The gate of JFET1 in the meantime is held at a constant voltage level by D4 and D5, two diode drops below V.sup.+. By selecting the circuit elements to generate a pinch-off (V.sub.p) voltage across R1, the same V.sub.p is established across the gate and source terminals of JFET1, turning it OFF.
To switch JFET1 ON, the gating voltage is removed from terminal 2, turning Q4 ON and Q2 OFF. This causes the differential switch current to flow through Q3, removing the voltage differential across R1. The gate and source of JFET1 are accordingly fixed at substantially equal voltages, turning the switch ON.
Theoretically, JFET1 will be kept OFF so long as the voltage across R1 is greater than V.sub.p. However, the various circuit elements of FIG. 1 are subject to process and temperature variations that have resulted in R1 being assigned a much lesser resistance value than would be necessary in the absence of such variations. This in turn has caused an excessive power consumption when the differential switch current is routed through R1.
The processing and temperature variations show up in several ways. First, R1 is typically subject to processing variations of up to 20% or more, and in the Precision Monolithics, Inc. device referred to above has a temperature coefficient of 2000 ppm/.degree.C.
The voltage across R1 may be expressed as follows: ##EQU1## where I.sub.DSS is the maximum drain current of JFET2, .beta., W and L are respectively the device constant, width and length of JFET2, and V.sub.p is the pinch-off voltage of JFET1 and JFET2. W is relatively constant, but L is usually sensitive to masking and etching, and .beta. and V.sub.p both vary with processing and temperature. The net processing variations to which I.sub.DSS is subject can be in the range of 9:1, and I.sub.DSS is subject to further temperature variations.
Accordingly, the voltage across R1 must be made large enough to accommodate all expected variations and still generate an adequate V.sub.p to turn JFET1 OFF. With a nominal V.sub.p of 1.9 volts, the voltage across R1 has typically been set at 7 or 8 volts. R1 thus consumes about 3 to 4 times more power than would be necessary if processing and temperature variations could be substantially eliminated, permitting the voltage across R1 to be established at a level only slightly greater than V.sub.p.